(1) Field of the Invention
This invention relates to a fabrication method of a trenched power semiconductor structure, and more particularly relates to a fabrication method of a self-aligned trenched power semiconductor structure.
(2) Description of the Prior Art
FIGS. 1A to 1C are schematic views showing a fabrication process of a typical trenched power semiconductor structure. As shown in FIG. 1A, firstly, a gate trench 120 is formed in a silicon substrate 110. Then, a gate oxide layer 130 is formed to line the inner surface of the gate trench 120. Afterward, a polysilicon layer is deposited on the upper surface of the silicon substrate 110 and an etching back step follows to remove the unwanted portion of the polysilicon layer so as to leave a polysilicon gate 140 in the gate trench 120.
After the formation of the polysilicon gate 140, as shown in FIG. 1B, a body implantation step is carried out to implant dopants into the silicon substrate 110 so as to form a body 150 surrounding the gate trench 120. Then, a source implantation step is carried out to implant dopants of different conductive type into the body 150 so as to form the source region 160 in the upper portion of the body 150. Thereafter, as shown in FIG. 1C, a dielectric layer 170 is deposited on the exposed surfaces of the silicon substrate 110 and fills the gate trench 120. Then, a contact window 180 for exposing the source region 160 is formed in the dielectric layer 170 and the body 150 by using lithographic and etching processes.
It is noted that the shrinkage of cell dimension of the trenched power semiconductor device is restricted by lithographic limitations. That is, due to the limitations of critical dimension for trench and contact window as well as tolerance required for alignment control, the distance between the gate trench 120 and the contact window 180 should be great enough to prevent the problems such as leakage current, variation of threshold voltage, or decreasing of avalanche ruggedness.
Accordingly, how to increase cell density of trenched power semiconductor structure under the limitations of critical dimension for trench and contact window as well as tolerance required for alignment control is an important issue to be resolved.